Northrop Grumman Corporation

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Principal ASIC Design Engineer/Sr. Principal ASIC Design Engineer

at Northrop Grumman Corporation

Posted: 5/9/2020
Job Reference #: 20013621
Keywords: modeling

Job Description

Northrop Grumman Mission Systems (NGMS) Advanced Capabilities sector is leading development of next generation high performance computing systems for Cyber and Intelligence Mission Solutions (CIMS). These systems are designed using our patented superconducting digital logic technology - Reciprocal Quantum Logic (RQL). On a gate for gate basis, RQL consumes orders of magnitude less power than CMOS while running at significantly higher clock speeds. Northrop Grumman is now advancing the technology in development of processors, memory subsystems, and large scale high performance computing systems.
 
We are seeking front-end ASIC design engineers for design and verification of full-custom digital and mixed signal Superconducting Circuits.  Must be proficient in Verilog, System Verilog or VHDL RTL coding, with experience writing functional test benches. An understanding of synchronous digital design concepts is also required, with the ability to create a functional verification plan based on requirements of the circuit.  Should be able to generate manufacturing test vectors and manufacturing test plan.  Knowledge of synthesis, SDC constraints, formal verification, and static timing is desired. Knowledge of scan insertion and ATPG is a plus.  Automated place and route and physical verification knowledge is a plus.  Must have strong written and oral communication skills.
This position can be filled at a Principal ASIC Design Engineer OR a Sr. Principal ASIC Design Engineer.  Qualifications for both are listed below:
CIMS
 


Qualifications

Basic Qualifications for Principal ASIC Design Engineer:  
  • Bachelor's degree in a technical area (BSEE or other Engineering discipline preferred) with 5 years of relevant experience (3 years with technical MS)
  • Experience with full product life cycle (requirements, design, implementation, test) of ASIC design
  • Working knowledge of the front-end ASIC design flow from RTL to gates (RTL coding, simulation, synthesis, static timing analysis, logic equivalence, DFT insertion)
  • Experience with some or all of the current ASIC design tools for all phases described above
    • Simulation – Mentor ModelSim, Cadence Incisive or Synopsys VCS
    • Synthesis – Synopsys Design Compiler, Cadence Genus or Cadence RTL Compiler
    • Static Timing – Synopsys Primetime or Cadence Tempus
  • Active TS/SCI security clearance with current polygraph
Basic Qualifications for Sr. Principal ASIC Design Engineer:  
  • Bachelor's degree in a technical area (BSEE or other Engineering discipline preferred) with 9 years of relevant experience (7 years with technical MS, 4 years with technical PhD)
  • Experience with full product life cycle (requirements, design, implementation, test) of ASIC design
  • Working knowledge of the front-end ASIC design flow from RTL to gates (RTL coding, simulation, synthesis, static timing analysis, logic equivalence, DFT insertion)
  • Experience with the current ASIC design tools for all phases described above
    • Simulation – Mentor ModelSim, Cadence Incisive or Synopsys VCS
    • Synthesis – Synopsys Design Compiler, Cadence Genus or Cadence RTL Compiler
    • Static Timing – Synopsys Primetime or Cadence Tempus
  • Active TS/SCI security clearance with current polygraph
 
Preferred Qualifications:
  • Advanced Degree - either MS or PhD
  • Experience with chip level integration and ASIC chip lead
  • Strong design automation skills
  • Experience in CAD design network, tool configuration, and data management
  • Familiarity with custom layout in Virtuoso, and physical verification (LVS/DRC) in Assura or Calibre
  • Familiarity with revision control and EDA standard formats used in cell/library development and modeling – Liberty (timing model),), SDC (Synopsys Design Constraints)
  • Proficiency with current ASIC design tools for all phases described above
    • Simulation – Mentor ModelSim, Cadence Incisive or Synopsys VCS
    • Synthesis – Synopsys Design Compiler, Cadence Genus or Cadence RTL Compiler
    • Static Timing – Synopsys Primetime or Cadence Tempus


Northrop Grumman is committed to hiring and retaining a diverse workforce. We are proud to be an Equal Opportunity/Affirmative Action Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO/AA and Pay Transparency statement, please visit www.northropgrumman.com/EEO. U.S. Citizenship is required for most positions.